1. Field of the Invention
The present invention relates to a semiconductor chip package, a connecting board, and a method of connecting multiple, stacked semiconductor chips.
2. Description of the Related Art
The electronics industry continues to seek products that are lighter, faster, smaller, multi-functional, more reliable and/or more cost-effective. In order to meet the requirement of the electronics industry, circuit chips are becoming highly integrated.
However, enhancing the integration density of chips is expensive and has technical limitations. Therefore, 3-D type semiconductor packaging technologies have been adopted. In general, a multi-chip package made by stacking a plurality of chips in a package is known. For instance, in a stacked package manufactured by a combination of two semiconductor memory devices, the memory capacity of the semiconductor is doubled. Chip stacking configurations may introduce difficulties such as a more complex manufacturing process and/or complications or limitations associated with increased package thickness.
In order to manufacture a multi-chip package using conventional ball grid array type packages, the upper chip is usually the same size or larger than the lower chip. A spacer is inserted between the chips, because the upper chip may contact one or more bonding wires of the lower chip. The spacer helps reduce or prevent electrical interference caused by one or more bonding wires of the lower chip contacting an underside of the upper chip.
Exemplary spacers used for manufacturing a multi-chip packages are shown in FIG. 1 and FIG. 2. FIG. 1 is a cross-sectional view of an example of a conventional multi-chip package.
The conventional multi-chip packages 10 and 20 of FIGS. 1 and 2, respectively, may include a printed wiring board 11, a lower chip 14 disposed on the printed wiring board 11 with adhesive 15, an upper chip 19 secured by liquid adhesive 17 including a plurality of insulating fillers 18 on the lower chip 14. In general, a bonding wire 16 is electrically connected to one end of each metal pattern 13 formed on the printed wiring board 11. The other end of the metal pattern 13 may be electrically connected to another electrical device, such as another electrical device at the rear side of the printed wiring board 11. The same or larger sized upper chip 19 compared with the lower chip 14 may contact the top of the bonding wire 16 during the upper chip 19 bonding process. Electrical interference may occur when the bonding wires 16 contact the underside of the upper chip 19.
As described above, a spacer, such as an insulating filler 18 may be inserted between the lower chip 14 and the upper chip 19. The insulating filler 18 allow sufficient height for the bonding wire 16 loops. The upper chip 19 may still be pressed down during a chip bonding process and/or wire bonding process, even though the height of the insulating filler 18 is sufficient. For instance, the wires 16 may be connected to bonding pads (not shown) on the upper chip 19 by thermal compression method.
FIG. 2 is a cross-sectional view of another example of another conventional multi-chip package 20. The conventional multi-chip package 20 of FIG. 2 may include a printed wiring board 21, a lower chip 24 secured to the printed wiring board 21 with adhesive 25, and an upper chip 29 secured by insulating adhesive tape 27 on the lower chip 24. Similarly, the bonding wires 26 may be affected by the underside of the upper chip 29 during a chip bonding process and/or wire bonding process. The insulating adhesive tape 27 can be inserted between the lower chip 24 and the upper chip 29, and the insulating adhesive tape 27 may have sufficient height for the bonding wire 26 loops.
In the conventional multi-chip packages 10 and 20, the upper chip 19 lower chip 14 arrangement has some limitations. The multi-chip package with two or more chips is vertically thicker due to the spacer, either the insulating filler or the insulating adhesive tape. In addition, increasing the number of mounting chips used in a conventional multi-chip package increases the likelihood of wire bonding failure, electrical failure, and/or reliability issues.